1. Field of the Invention
The present invention relates to testing of integrated circuits, and more specifically to a method and apparatus for increasing possible test patterns which can be used with sequential scanning techniques to perform speed analysis.
2. Related Art
Speed analysis generally refers to measuring the delays which are encountered in receiving signals at the end of corresponding paths in integrated circuits. The measurements are usually performed to ensure that each generated signal is propagated (or reaches) to the corresponding ends of paths within any time limits as may be necessary for the operation of an integrated circuit at a specific clock frequency. Of particular concern are the specific path(s) which operate with longest delay(s), and the path is commonly referred to as a critical path.
Various approaches are known in the prior art to perform speed analysis. In one approach commonly referred to as functional testing, various bits (forming a test pattern) are provided on various inputs of an integrated circuit, and the outputs are examined for accurate functional operation of the circuit. In addition, the speed analysis may also be performed by measuring the time required to receive the outputs at the ends of the respective paths.
One problem with functional testing based approaches is that specific desired paths (e.g., critical path) may not be excited (signal generated at one end and propagated to another end of the path) with a set of test patterns. Accordingly the delays encountered on such paths may not be measured when only that set of test patterns are used. In addition, determination of a test pattern which would excite a specific desired path, may present challenges.
Sequential scanning techniques provides an alternative approach to perform speed analysis on specific paths. As is well known in the relevant arts, Delay Fault Automatic Test Pattern Generation (DFATPG) is an example of such a sequential scanning approach. In a typical scenario, the memory elements (e.g., flip-flops) are connected in sequence, and a desired sequence of bits (“test pattern”) is sequentially scanned (scan order) into the memory elements.
The test pattern (and the circuit architecture) generally needs to be designed such that a serial shift of the test pattern in all the memory elements causes a transition (logical 0 to 1 or vice versa) on only a memory element connected at one end of a path of interest. As the content of the other memory elements may not change, the other memory elements may not affect the signal propagation on the path of interest, and the delay in the propagation of the transition over the path of interest may be reliably measured using DFATPG.
From the above, it may be appreciated that a DFATPG test pattern may need to be designed such that a shift of the test pattern changes the bit value of only desired specific memory element (connecting at one end of a critical path), and not others. A test pattern satisfying such a requirement may be referred to as a “robust test pattern” in the DFATPG environment.
Attempts have been made to design integrated circuits which satisfy the robustness requirement for test patterns in DFATPG approach. In one prior approach, the memory elements are connected in such a sequence that all the memory elements storing one logical value are connected in one direction of a subject memory element (coupled to an end of the critical path), and memory elements with another value are connected in the another direction.
One problem with such an approach is that the approach imposes (or requires) a specific order (scan order) in which the memory elements are to be connected, and the corresponding connectivity requirement may pose challenges in layout and routing while designing an integrated circuit. In addition, different test patterns may impose conflicting scan orders. Accordingly, the approach may not be suitable for at least some environments.
In another approach, which may not require connectivity of memory elements in scan order, an additional memory element (“dummy memory elements”) may be used in the middle of sequence of memory elements, for example, to avoid undesirable changes in other memory elements which may affect the subject critical path.
As an illustration, it is assumed that a transition is desirable in one of the sequence of memory elements and such a transition can be attained by a shift operation. Assuming further that such a shift would shift-in an undesired value from one memory element to an adjacent memory element, a dummy memory element may be used in between the two elements. The dummy memory element can be pre-set to a value to ensure that the shift operation does not cause a transition in the adjacent memory element and thus retaining the off-path input.
However, one disadvantage of such an approach is that a large number of memory elements may be required to support, for example, excitation of various paths, and the resulting consumption of space (on the integrated circuit) and power consumption may be unacceptable.
Thus, it may be appreciated that the robustness requirement in DFATPG leads to various design constraints (e.g., routing in the first approach described above, and the need for dummy memory elements in the second approach) even when performing speed analysis on a single path of interest. The constraints are compounded when several paths need to be analyzed, as is often the case in design of complex integrated circuits.
A reason for the presence of such constraints is the small number of acceptable test patterns (for analyzing each path) forced by the robustness requirement in DFATPG. Accordingly, what is needed is a method and apparatus for increasing number of possible test patterns which can be used with sequential scanning techniques to perform speed analysis.